Electrostatic discharge (ESD) control measures are typically employed in fabrication facilities for semiconductor devices. These control strategies are typically employed in the fabrication facilities external to the tools, however, currently, there are no generally applied protocols for neutralizing the buildup of electrical charges within the vacuum regions of the tools themselves.
The buildup of charge on tool structures may be expected to be of concern whenever high voltage is employed near a wafer pad in a tool. For example, ion implants are used to introduce dopants into the underlying semiconductor material to produce the structural elements of the transistors constituting the integrated circuit device being fabricated. Shallow junction formation requires implants at relatively low beam energies, on the order of 0.2 to 5 kilo electron volts (keV). To compensate for divergence of the ion beams due to space charge effect, an electrostatic focusing lens may be employed, which lens may be deployed close to the pad supporting the wafer during the implantation.
Additionally, the wafer being fabricated may be supported on a pad formed from an insulating material. These feature sizes of the transistors and associated interconnect forming the circuitry of the integrated circuit device have become smaller, the components of the tool have evolved accordingly. Thus, insulating materials, for example, alumina or elastomeric polymers may be used to support the wafers to prevent scratching, as well as reduce particulate contamination. Also, electrostatic clamping has supplanted mechanical clamping for similar reasons and such pads are suitable use with this clamping mechanism.
Exposure of the insulating pad to high voltages from, for example, focusing lens in proximity thereto, may induce long term electrostatic polarization on the pad. As the pad becomes electrically polarized, which may bear a surface voltage on the order of 10 kilo volts, an undesirable adhesion of the wafer to the pad may be observed. In extreme cases, the electrostatic bonding of the wafer to the pad may be large enough that the forces required to lift the wafer from the pad produce stresses in the wafer sufficient to break the wafer. An early manifestation of the polarization of the pad, before the polarization has reached the extreme values where the integrity of the wafer is jeopardized, is misalignment of the wafer on the pad. During the wafer loading process, the electrostatic forces between the wafer and the pad may result in an observable misalignment of the wafer and pad since the wafer cannot slide freely on the pad. The misalignment is detected by the wafer handling equipment and processing of the wafers cannot be performed under these circumstances. Retrieving the misaligned wafer is usually time consuming since it has to be removed manually from the pad.
In the case when the charging-up is found at the end of the implant, the wafer cannot be lifted up by the wafer lift pins due to the electrostatic force between the pad and the wafer in the wafer unloading process. The wafer remains adhered to the pad until the force exerted by the lift pins exceeds the polarization force adhering the wafer to the pad, at which time, the wafer abruptly separates from the pad. In such cases, the wafer may be popped up from the wafer pad causing it to be offset from its normal position and the wafer transportation mechanism cannot retrieve the wafer automatically. Manual intervention is then required to remove the wafer from the wafer pad.
In either cases, the product wafer is at risk of breakage and production time wasted. Thus, the polarization does not need to rise to the levels where the integrity of the wafer is jeopardized before deleterious affects on the throughput of the device fabrication process occur.
Consequently, there is a need in the art for techniques to control the buildup of electrostatic charge, and the concomitant ESD, in a fabrication tool, and in particular, in ion implantation tools in which structures, for example, focusing lenses, are operated in proximity to the pads supporting the wafers being fabricated.